The present invention relates to a counter for various semiconductor devices and logic circuit systems, and more particularly, to a counter that can prevent a code overflowing.
An overflow occurs when a counter counts a code as described below with reference to FIGS. 1 to 3.
FIG. 1 is a block diagram of a conventional N-bit counter.
Referring to FIG. 1, the conventional counter counts a code OUT<0:N-1> in response to a flag signal FLAG and a strobe signal STROBE. The strobe signal STROBE is a signal that strobes the counter. The counter increases or decreases a code value whenever the strobe signal STROBE is activated. The flag signal FLAG is a signal that instructs the counter to increase or decrease the code value. The counter increases the code value when the strobe signal STROBE is inputted while the flag signal FLAG is at a logic high level. On the other hand, the counter decreases the code value when the strobe signal STROBE is inputted while the flag signal FLAG is at a logic low level. In FIG. 1, an enable signal ENABLE is a signal that enables or disables the operation of the counter.
FIG. 2 is a timing diagram illustrating a high overflow of the counter.
Referring to FIG. 2, if the strobe signal STROBE is continuously inputted while the flag signal FLAG is at a logic high level, the code value of the code OUT<0:N-1> increases to “111 . . . 1”. Thereafter, if the code value is increased one more time, the code value of the code OUT<0:N-1> becomes “000 . . . 0”. This phenomenon is called a high overflow of the counter.
FIG. 3 is a timing diagram illustrating a low overflow of the counter.
Referring to FIG. 3, if the strobe signal STROBE is continuously inputted while the flag signal FLAG is at a logic low level, the code value of the code OUT<0:N-1> decreases to “000 . . . 0”. Thereafter, if the code value is decreased one more time, the code value of the code OUT<0:N-1> becomes “111 . . . 1”. This phenomenon is called a low overflow of the counter.
The overflow of the code may output a wrong result code OUT<0:N-1> if an input value is more than or less than a value that can be expressed with N bits. Therefore, there is a need for a circuit that can stop increasing or decreasing the code OUT<0:N-1> of the counter from “111 . . . 1” or “000 . . . 0”.